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Analog IPs Automate Integration, Tune to Fab Nodes

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System-on-chip (SoC) designs with heterogeneous voltage domains are increasingly moving away from custom analog IP to automated implementation so design engineers don’t have to worry about schedule slips caused by manual analog customizations. It also saves chip designers several months in the design process, while making analog circuits less susceptible to on-chip surroundings.

It’s important to note that automatically generated analog IP isn’t synonymous with off-the-shelf analog IP. Rather, analog IP generators bring the previously generated custom-design blocks into the design flow and employ specialized tools to tailor a suitable IP within hours. That, in turn, saves a lot of integration time and effort.

One of the key challenges that semiconductor engineers face when analyzing their solutions, however, revolves around how much analog designs can shrink when moving from one chip manufacturing process node to another. In other words, there are certain analog building blocks that don’t scale adequately to smaller IC manufacturing nodes. Moreover, while digital logic is getting cheaper in modern SoCs, not all analog functions can be incorporated economically.

“Once you start choosing different processes, speed, power consumption and cost also become key design considerations,” said Ron Lowman, strategic marketing manager for IoT at Synopsys. “While some analog designs can take advantage of standard CMOS-based designs, smaller IoT designs do require special process technologies, which becomes a key factor when designing analog IP.”

Figure 1: The analog/mixed-signal IPs (on the bottom left) of the SoC design must be qualified for the fab’s process node. (Source: Synopsys)

At this crossroads, IP suppliers’ closely-knit relationships with semiconductor fabs matter a lot. Take the case of Analog Bits, which provides fundamental building blocks of high-performance analog and was recently acquired by chip design service provider SEMIFIVE. Analog Bits joined the Intel Foundry Services (IFS) and its IP Alliance program in early 2022 to support the Intel 16-nm process in clocking, sensor and I/O.

Analog Bits also announced the availability of its IP portfolio for GlobalFoundries’ (GF) 12-nm 12LP process node, as well as unveiled plans for analog and mixed-signal IPs catering to TSMC’s 4-nm and 3-nm process nodes.

Future challenges of analog IP

While transitioning from the highly manual analog design process to the automated generation of code for analog IP blocks saves a lot of time and integration effort, it’s not without challenges—especially when chip foundries continuously move to smaller manufacturing processes.

Semiconductor fabs are introducing new process technologies every six months, and these aren’t just scaled-down versions of the previous node; they are increasingly complex and structurally different from the previous node. One example of this dynamic is the new N3 FINFLEX technology from TSMC, introduced during the foundry’s 2022 Symposium.

Transitions to smaller nodes have been seen as a major stumbling block for the analog design realm for quite some time. That makes recent announcements from IP suppliers to support 4-nm and 3-nm process geometries a notable premise. When it comes to smaller nodes primarily designed for digital, however, analog engineers will have to do things differently.

Transitioning from FinFET to gate-all-around (GAA) manufacturing process technology in advanced nodes will also bring unique engineering challenges like capacitance compensation. As a result, analog integration at these advanced nodes will require much higher levels of mixed-signal circuit innovation.

Furthermore, analog and mixed-signal designs on 4-nm and 3-nm nodes will demand a new breed of toolchains to complement the traditional SPICE simulators.

“Analog simulators need to constantly enhance their model parsers to support the latest and greatest process nodes,” said Sathish Balasubramanian, head of product, marketing and business development for the AMS division at Siemens EDA. “This is critical, as analog simulators are used to characterize standard cell libraries, which will become foundational digital building blocks for new chips.”

Figure 2: Analog/mixed-signal IPs at smaller nodes call for a new generation of design toolchains. (Source: Siemens EDA)

Besides EDA toolchains, toolkits provided by analog and mixed-signal IP suppliers are also crucial to fast-track, simplify and re-risk the design process. That means IC developers don’t have to figure out how to incorporate these IP building blocks in their SoC designs.

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