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Cadence expands verification IP portfolio

Cadence has added 13 new verification IP (VIP) offerings for developing SoCs for automotive, hyperscale data center, and mobile applications. The VIP platform also helps developers keep pace with the latest industry standards, including Arm AMBA 5 CHI-F, Universal Chiplet Interconnect Express (UCIe), GDDR7, DDR5 DIMM, MIPI A-PHY, MIPI SoundWire I3S, and USB4 2.0 interfaces.

The VIP portfolio gives customers access to a consistent application programming interface across all VIP with complete bus function models, integrated protocol and timing checks, and coverage models. What’s more, all VIP solutions include TripleCheck IP Validator, which provides a specification-compliant verification plan linked to coverage models and a test suite to ensure compliance with the interface specification.

In addition, the VIP portfolio supports the expanded System VIP platform for chip-level verification automation. According to Cadence, SoC verification automation with System VIP increases verification efficiency by as much as 10X compared to manual SoC verification.

To learn more about the Cadence VIP portfolio, click here.

Cadence Design Systems 

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