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Chiplet Standardization Requires Innovative Approach

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This week’s Chiplet Summit underscores the rapid evolution of the ecosystem around multi-die chip design. Such a gathering of experts emphasizes how this area has quickly emerged as a critical part of every leading-edge silicon development strategy, an inflection point in a roadmap long guided by Moore’s Law and now being driven to find innovation methods to continue the required scaling.

The success of chiplet architectures will depend on the interconnect between the chiplets. It must provide massive bandwidth and great energy efficiency, and it must require minimal beachfront and die area. Standards and interoperability are key, and initiatives like Universal Chiplet Interconnect Express (UCIe) and JEDEC are putting important processes in place to guide development efforts.

The state of die-to-die interconnects

Today, there are two fundamental approaches to achieving the technology objectives mentioned above.

The first approach is to simply extend the number of interconnects—copper lines—between chiplets, using advanced packaging technologies like silicon interposers or embedded silicon bridges. These links can be driven by large inverters but mostly at relatively lower rates—about 1 to 16 Gbps per line. They get higher bandwidth by leveraging very fine bump and line pitches, allowing huge numbers of lines between chiplets.

Unfortunately, advanced packaging is very complex to fabricate and assemble at the large sizes required by high-performance systems-in-package. Wafer testing to screen the chiplets—with those extreme pitches—for known-good dies is limited and leads to yield issues. It is proprietary, limiting the ability to move designs between fabs. And the very short reach—2 to 3mm—of advanced packaging interconnects between chiplets can greatly complicate thermal design, especially if some chiplets, such as HBM DRAM dies, must be protected from high temperatures of hot processor chips next to them.

The second approach is to use SerDes and high-speed serial transceivers to move data at very high rates—16 to 64 Gbps per line. This can drastically reduce the number of interconnect lines necessary for a given aggregate bandwidth. And with relaxed pitches and properly tuned transceivers, it can work over organic substrates as well as over silicon interconnects.

Anyone familiar with the power-hungry and dazzlingly complex transceiver blocks on FPGAs and networking PHYs may at once question the feasibility of this approach for chiplets. Banks of these transceivers would require far too much beachfront, die area and power for any but the largest chiplets.

Chiplets have an inherent advantage

There has been work on addressing these challenges for the past several years, including my involvement with early work on chiplet architectures about six years ago. I had already had some success in high-speed serial communications from my work at Stanford, Velio Communications, Rambus and Aquantia, and those learnings led us to make a key observation about die-to-die connectivity. Compared with the general case of communications across long spans of co-ax or twisted pairs, the links between chiplets had many advantages. They were short—typically no more than a couple of centimeters. The environment was well-controlled, with low noise, controlled impedances and minimal reflections. These facts meant the transceiver design could be greatly optimized for such a specific channel for best power and area.

Eliyan CEO Ramin Farjadrad.
Eliyan’s Ramin Farjadrad

Differential signaling was not needed. Nor were sophisticated clock recovery or embedded link control signals. Because additional pins were readily available, separate pins for source- synchronous clocks and for side channel controls worked well. In this controlled environment, single-ended NRZ signaling could reach very high speeds, so the complexities of multi-level signaling, like PAM-4, were unnecessary, as was a sophisticated error-correction scheme.

Careful modeling, refining and testing resulted in a chiplet-optimized serial architecture aimed for use originally over organic substrates and, later, an expanded signaling scheme to support the silicon substrates of advanced packaging.

This was the origin of Bunch of Wires (BoW), which was adopted in two versions as open interconnect standards by the Open Compute Project (OCP). A third, faster level of the PHY that leverages simultaneous bidirectional NRZ signaling was then owned by Marvell Technologies (through its acquisition of Aquantia in 2019) and was implemented in production at a 14-nm process that is operating today in millions of commercial systems.

Refined and renamed Nulink, this version of BoW, which is effectively a BoW superset, has been spun out of Marvell into a new venture, Eliyan. A test chip in TSMC 5 nm with considerable improvements in power and bandwidth has successfully taped out, with silicon scheduled for the second quarter.

Many protocols

This protocol-agnostic PHY layer can transport a wide range of traffic, including PCIe, using a simple adapter and the emerging Compute Express Link (CXL) protocol. Thus, it can provide the physical layer for a universal chiplet interconnect architecture serving many types of traffic between many types of chiplets. And because it has a fully optimized implementation for this purpose, it can achieve performance and energy efficiency comparable to the designs that rely on silicon interposers or bridges—but over conventional, low-cost organic package substrates.

Our innovation was not the only development to come out of the BoW standards at OCP. Starting independently, another team used the similar interconnect principles of BoW to formulate another PHY standard: UCIe. We believe our approach, as a superset of BoW, is an excellent path to implementing a fully UCIe-compliant chiplet interconnect architecture.

We are prepared to provide the PHY for a universal chiplet interconnect architecture, offering state-of-the-art performance and power while freeing chiplet-based systems from the need for silicon interposers or embedded silicon bridges and their associated limitations, high complexities and costs. We know well that a standards-based approach through organizations like OCP, UCIe and JEDEC is critical to aligning the ecosystem. At Eliyan, we are on board with these initiatives and are ready to contribute our expertise and technology to advance and accelerate the adoption of chiplets in the industry.

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