Job Description: Role and Responsibilities
As an Engineer responsible for CPU Random Tools for stress verification, you will work on a sophisticated Random Instruction Sequences (RIS) tool. With a combination of techniques, the tool verifies the functionality of our CPU cores, being designed in Austin (US), Cambridge (UK), Chandler (US) or Sophia Antipolis (FR). The existing team ensures addition of new architecture features, its customization to specific CPU cores, and provides support.
You will be based in Arm’s Bangalore design centre in India.
- As Verification Engineer, your role will cover the development of the tool from development to deployment, and accountable for:
- Understanding the intricacies of the CPU micro-architecture and defining how to push the test boundaries;
- Architect and develop solutions to improve the generation of stimuli to produce programs to stress our next generation CPUs;
- Implementing and supporting the tool, from the early stages of CPU development to product maturity.
- Problem Ownership and ability to work from abstract requirements
- Good communication and presentation skills
- Self-motivated and willing to take up additional responsibilities
- Quick learner with a strong desire to learn and develop new skills
Qualification and Experience
- B.Tech/B.S. or MTech/M.S. in Computer/Electronics Engineering or Computer Science from a reputed institute
- 3-6 years of stable proven experience with significant project contributions
- You hold experience in software design, and should be comfortable working with low-level hardware
- You have good solid understanding of programming languages, such as C and Python
- You are knowledgeable about CPU architecture and micro-architecture concepts
- You are able to understand assembly language (ASM)
- You have strong interpersonal skills and ability to work well as part of a team with the willingness to tackle varied technical challenges.
- Fundamentals of Processor Architecture.
- Basics of ARM Architecture.
- Familiarity with EDA tools and Hardware Design Verification.