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EUV Alternative Speeds Up Chip Production

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Applied Materials has introduced its new Centura Sculpta pattern-shaping system that promises to provide a cost-effective alternative to extreme ultraviolet (EUV) lithography double patterning used to print dense interconnect lines and vias. As a result, the solution can reduce the number of EUV steps, production complexity and costs while potentially improving yields.

By now, all three leading chipmakers—Intel, Samsung and Taiwan Semiconductor Manufacturing Co. (TSMC)—have either started to use EUV lithography tools for mass production or are about to. Lithography scanners are certainly the rockstars of wafer fab equipment, and EUV lithography tools are set to be instrumental for chipmakers for years to come. But there are other tools that are vital to continuously shrinking transistor dimensions, increasing performance and reducing power consumption, such as Applied Materials’ Centura Sculpta pattern-shaping system.

Applied Materials’ Centura Sculpta.
Applied Materials’ Centura Sculpta (Source: Applied Materials)

Centura Sculpta pattern-shaping system

To keep advancing transistor performance, power consumption and density, chipmakers must adopt more sophisticated process technologies with tighter critical dimensions. Usage of dual EUV exposure is inevitable to print smaller features with 3-nm, 2-nm and thinner nodes. But double EUV patterning is expensive, lengthy and resource-consuming.

Advantages of pattern-shaping tools at a glance.
Advantages of pattern-shaping tools at a glance (Source: Applied Materials)

Applied Materials’ Centura Sculpta is a pattern-shaping machine that stretches the shapes patterned by an EUV scanner using a special algorithm in any chosen direction across the X-axis to shrink the space between features and increase pattern density. Elongating existing shapes removes an EUV litho-etch process loop that takes time, consumes energy and materials and costs money.

Pattern-shaping alternative to EUV double patterning for interconnect lines.
Pattern-shaping alternative to EUV double patterning for interconnect lines (Source: Applied Materials)
Pattern-shaping alternative to EUV double patterning for vias.
Pattern-shaping alternative to EUV double patterning for vias (Source: Applied Materials)

The algorithm resembles optical proximity correction techniques already used at fabs to enhance resolution of fab tools. Because the process does not involve the second mask, there are no alignment errors and associated problems, according to the company. As the toolmaker explains it, the whole process resembles etching, albeit using a different tool.

Unlike lithography scanners, Centura Sculpta uses angled reactive ribbon beam to precisely sculpt the patterning materials stack. Because the machine does not use any photomasks, the material removal process is not prone to alignment errors, which promises higher yields compared with usage of EUV double patterning for interconnect lines and via pitches, according to Applied Materials.

“The Sculpta system uses a unique angled reactive ribbon beam to sculpt the patterning materials stack,” the company explained in a YouTube video. “As the sidewalls are exposed to the beam, chemically reactive species and radicals precisely remove patterning material at the nanometer precision to enhance the shapes. The wafer can be rotated in any direction to create desired shapes without any additional lithography steps.”

Process flow with and without pattern shaping.
Process flow with and without pattern shaping (Source: Applied Materials)
General benefits of using pattern shaping instead of another EUV exposure.
General benefits of using pattern shaping instead of another EUV exposure (Source: Applied Materials)

The tool uses existing chemistry already used at the fab to remove materials and elongate the shapes of trenches or vias, so it can presumably be deployed fairly quickly and without necessity to rebuild a cleanroom. The company admits that its Centura Sculpta is a large machine, but it is not as big as an EUV scanner, so it should be compatible with the vast majority of existing fabs.

While EUV double patterning is expensive, its usage can reduce stochastic defects that EUV lithography is known for. Although Centura Sculpta was designed to elongate lines across the X-axis, it can fix certain stochastic defects by removing unnecessary material, according to Applied Materials.

Yet the system cannot naturally fix defects that emerge when material is missing. Additionally, Centura Sculpta will not replace double-patterning EUV when forming metal pitches on critical layers. For example, the system can do nothing with dimensions of metal pitches and additional EUV LE loops they need.

Therefore, Centura Sculpta does not replace EUV double patterning completely from production flow, but it reduces its usage—thus saving time as well as hundreds of millions of dollars in capital ($250 million per 100,000 wafer starts per month), costs per wafer and environmental impact.

With a reduced number of EUV exposures required, chipmakers can optimize usage of expensive Twinscan NXE scanners and either reduce the number of EUV tools they need for required production capacity or increase their production capacity without increasing the number of EUV scanners.

Centura Sculpta implementations

Because Applied Materials’ Centura Sculpta is a unique tool, the company’s leading logic customers are currently studying the system, according to the company. So far, only Intel has announced plans to use the machine for its Intel 20-A fabrication process in 2024–2025. TSMC declined to comment whether it is testing the company’s pattern-shaping machine.

“As Moore’s Law drives us to ever-greater compute performance and density, pattern shaping is proving to be an important new technology that can help reduce manufacturing cost and process complexity, [as well as] conserve energy and resources,” said Ryan Russell, corporate vice president for logic technology development at Intel. “Having collaborated closely with Applied Materials in the optimization of Sculpta around our process architecture, Intel will be deploying pattern-shaping capabilities to help us deliver reduced design and manufacturing costs, process cycle times and environmental impact.”

Speaking of insertion of the company’s Centura Sculpta into the flow, it should be noted that it does not require changes of design rules, according to the company. In fact, it could even be used for existing production technologies, but because chipmakers already have equipment, they must make chips now, so they are not going to use the new tool for contemporary production nodes.

“Changes to design rules are not required,” said Steven Sherman, managing director and general manager of the advanced products group of the semiconductor products group at Applied Materials. “Sculpta is producing the same patterns using the same design rules that a chipmaker would produce and use without Sculpta. Sculpta is being purchased for emerging nodes that would require EUV double patterning but can use Sculpta to accomplish the same results at lower fab capital cost and per-wafer manufacturing cost. That said, the product could be used at existing nodes, but that’s not the focus, as chipmakers have already bought the equipment for that production.”

The tool can provide several benefits beyond removing EUV double patterning for dense interconnect lines and vias, so its adoption will likely depend on how fast chipmakers learn how to use this all-new capability.

For now, Centura Sculpta can achieve tip-to-tip spacing of 15–20 nm without using EUV double patterning, which is how Applied Materials’ customers use the tool today (albeit not for high-volume manufacturing, but rather for various experiments), according to the company. Yet Applied Materials believes it can get to 5- to 10-nm tip-to-tip dimension over time when such resolution is needed, perhaps with high-numerical–aperture (NA) EUV insertion several years down the road.

ASML, the only maker of EUV scanners, welcomed the Centura Sculpta system but said that ASML, as well as chipmakers, must learn all its benefits and how to better use it.

“We hope it can be an additional tool to further improve EUV-based patterning,” said Sander Horman, a spokesman for ASML. “Our understanding is that Applied Materials expects the technology to be available for high-volume manufacturing within two years. Our belief is that this time must be used to validate that the technology can improve patterning for some of the shapes mentioned by Applied, without any side impact on all the other shapes composing a full die. We must also understand the applicability to highly irregular structures—that are typical for logic—and to uniformity over the wafer. In the coming months, we will work whenever needed with customers to see what benefit it brings.”

Two ways of shrinking

To achieve transistor density documented for their latest process technologies, chipmakers must print features with certain dimensions of fin pitches, contact gate pitches, minimum metal pitches and dense interconnect tip-to-tip space pitches. Chipmakers tend to advertise minimum sizes of M0 metal pitches, but tiny tip-to-tip spaces are equally important.

“Tip-to-tip dimensions are important because the tighter your tip-to-tip dimension is, the tighter you can pattern your vias and the vents, and ultimately the tighter you can pack your devices underneath the interconnects,” Sherman said.

Pitch-scaling roadmap by Applied Materials.
Pitch-scaling roadmap by Applied Materials (Source: Applied Materials)

Contemporary EUV scanners, such as ASML’s Twinscan NXE:3400C with 0.33 NA optics, offer an achievable critical dimension of approximately 13–16 nm for high-volume manufacturing—a resolution that is good enough to print a 26-nm minimum metal pitch, as well as an approximate 25- to 30-nm tip-to-tip interconnect space pitch with a single exposure patterning. This allows chipmakers to use existing manufacturing tools for 7-nm/6-nm (circa 36- to 38-nm metal pitches) as well as 5-nm/4-nm (about 30- to 32-nm pitches) production nodes relying on single exposure patterning.

While chipmakers tend to shrink metal pitches aggressively, they do not apply so much attention to interconnect tip-to-tip spaces and sometimes even sacrifice them, according to Applied Materials. Nowadays, metal pitches are so tiny and interconnect pitches are so dense that chip designers and mask shops must split high-density patterns in half and use two photomasks and two EUV exposures to comply with the resolution limits of EUV scanners.

“For a line-space pattern of about a 32-nm pitch, the tightest tip-to-tip space you could pattern with a single mask is about 25 to 30 nm,” Sherman said. “But the tip-to-tip that designers really want and need for today’s tightest critical layers is closer to 15 to 20 nm, and for that, you need to use double patterning.”

An example of EUV double patterning for interconnect lines.
An example of EUV double patterning for interconnect lines (Source: Applied Materials)
An example of EUV double patterning for vias.
An example of EUV double patterning for vias (Source: Applied Materials)

Over time, things will likely get harder. At 3 nm, metal pitches will shrink to about 21–24 nm, and at 2 nm, they are expected to be in a range of 18–21 nm, according to an ASML presentation that cites imec. Interconnect lines and vias pitches will have to get denser, too, which means usage of double patterning.

“[Chipmakers are] doing everything they can and play all kinds of lithography tricks to optimize resolution in the Y direction only to get the tightest metal-pitch line-space pattern they possibly can,” Sherman said. “So as you play those lithography tricks in the scanner and enable tighter and tighter metal pitches, you actually sacrifice resolution in the other direction—in the X direction. As we shrink to tighter and tighter metal-pitch line spaces, the tip-to-tip spacing that we can pattern gets worse.”

Logic-scaling roadmap outlined by imec and presented by ASML.
Logic-scaling roadmap outlined by imec and presented by ASML (Source: ASML)

To make chips using a 3-nm–class fabrication process, chipmakers must either use double patterning with 0.33 NA EUV tools or adopt next-generation high-NA EUV tools with 0.55 NA optics that promise to enable a resolution of about 8 nm. But while 3-nm–class nodes are already used by TSMC and Samsung Foundry for high-volume production, high-NA tools are at least a couple of years away.

As a result, chipmakers must use double patterning with EUV for their latest nodes to make metal pitches smaller and shrink tip-to-tip spacing to enable further scaling of performance, power and area (PPA).

An example of an EUV double-patterning process flow.
An example of an EUV double-patterning process flow (Source: Applied Materials)

A double-patterning EUV approach brings up a whole slew of new challenges, which includes added costs and a lengthened product cycle that is already 4,000 steps long. Applied Materials says that in addition to one more EUV lithography step (which costs $70 per wafer per layer) and an additional photomask (reticle), EUV double patterning adds chemical-vapor–resist film deposition, chemical mechanical cleaning (chemical oxidation and mechanical abrasion), photoresist deposition and removal, an eBeam metrology (to adjust the wafer and the second mask), patterning film etching and wafer cleaning. Extra steps mean additional wear-out for equipment, which translates into additional capital expenditures. Essentially, to keep PPA scaling, chipmakers must sacrifice costs and time.

“You always have to deposit patterning films and photoresist—there is always metrology associated [with] it,” Sherman said. “With each lithography step, you always have an etch step and some cleans. The multi EUV is effective at getting the dimensions you want on the wafer, but there are undesirable consequences. … Any alignment errors that remain after lithography and get etched onto the wafer will lead to performance problems and power issues. If the alignment is really bad, it will end up being yield.”

Undocumented feature: fighting stochastics

While initially designed to replace usage of EUV double patterning, Applied Materials’ Centura Sculpta can do other things, too.

EUV is known for the so-called stochastic effects caused by sparse EUV photon-absorption density in EUV resists. Stochastic effects result in defects like random bridge defects or poor line-edge roughness, among other things. Such defects are random by nature and are hard to find, begging the need for advanced inspection tools. While there are attempts to predict defects, they cannot be eliminated completely.

Four major stochastic effects and their percentage of EPE error budget.
Four major stochastic effects and their percentage of EPE error budget (Source: Fractilia)

ASML and other companies in the semiconductor production ecosystem have devoted time and effort to improve resists, masks and etch technologies to address stochastics.

“Over the last few years, we have worked with many partners on resist, mask and etch technologies for EUV,” ASML’s Horman said. “Improved resist sensitivity, imaging contrast, etc., have all resulted in significant gains in productivity or imaging performance.”

To some degree, double patterning can solve these problems, such as when a high-density pattern is split in two. Each mask does not have to use the smallest features possible and EUV scanners do not have to achieve their lowest resolution, which reduces stochastics. Moreover, as resists get better, fewer stochastic defects emerge.

“Double patterning is used whenever pattern features are less than the resolution capability of the exposure tool/resist,” said Bruce Fienberg, a spokesperson for Intel. “Managing stochastic variation is part of how decisions are made on the need to split the layers with additional EUV exposures to ensure a high-yield manufacturable process. So as scaling progresses and the density of features increases, there is a greater sensitivity over time to defects per unit area.”

Fienberg confirmed that usage of pattern-shaping systems like Centura Sculpta can reduce the number of stochastic defects significantly even compared with EUV double patterning but did not elaborate.

Furthermore, metal pitches will shrink and interconnections will get denser with 2-nm–class technologies (this is when Intel starts using Centura Sculpta), so fabs will keep using EUV double patterning.

“One approach to double patterning allows the pitch to be relaxed, resulting in fewer stochastic defects,” said Chris Mack, CTO of Fractilia, a company specializing in stochastics control. “But the pressure for scanner productivity with double patterning will be immense, possibly forcing fabs to lower the exposure dose to such levels that stochastic defects increase.”

Because Centura Sculpta is designed to replace EUV double patterning and the way it works does not create any stochastic defects, it reduces the number of stochastic defects on the wafer.

“We are going to basically remove materials, so the little protrusions you might get out the side wall, we could remove those, effectively improving line-edge roughness,” Sherman said. “It is another application that our customers are very interested in. We are working with them, and I would say it is in development. We are not ready to claim that we can actually realize the benefit in high volume, but it is an active area of development.”

Indeed, Centura Sculpta is a brand-new tool that is currently only positioned to remove an EUV litho-etch process loop when forming dense interconnect and via pitches. All its other benefits are undocumented and may be years away.

“Applied Materials has pushed this technology as a way to avoid one or more EUV double-patterning steps, but that is only the marketing position that they chose to emphasize,” Mack said. “It is possible that EUV double patterning will never happen with or without Centura Sculpta. It is also possible that Centura Sculpta could be used just to make EUV single patterning better, enabling, for example, a 3-nm node shrink in the tip-to-tip spacing at the same pitch. This could be quite valuable if it results in both higher yield and smaller die size. This represents Applied’s biggest challenge—how fast can Centura Sculpta get integrated into the flow? If it requires new design rule, then when can a company like TSMC offer it to their customers?”

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