A 24-Gb/s Graphics Double Data Rate 6 (GDDR6) PHY IP core from Rambus enables a high-bandwidth memory interface for AI/ML, graphics, and networking applications. At 24 Gb/s per pin, the GDDR6 PHY offers a maximum bandwidth of 96 GB/s for each GDDR6 memory device. It can be paired with the Rambus GDDR6 digital controller IP to provide a complete GDDR6 memory interface subsystem.
Available in advanced FinFET nodes for ASIC or SoC integration, the GDDR6 PHY IP core is fully compliant with the JEDEC GDDR6 (JESD250C) standard and supports two independent 16-bit–wide channels. The PHY leverages the manufacturer’s high-speed signal integrity and power integrity expertise and is optimized for systems requiring high-bandwidth and low latency, such as generative AI.
A DFI 3.1 style interface allows easy integration of the PHY core with the memory controller. While the Rambus GDDR6 PHY and GDDR6 controller can be used together, these cores can also be licensed separately to work with third-party GDDR6 controller or PHY solutions. The Rambus GDDR6 PHY is supplied as a fully characterized hard macro (GDSII), along with complete design views and documentation.
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.