How gate driver enables a wide range of battery voltages

When designing a product portfolio with a wide range of voltage and power requirements, finding a single driver design solution to serve the full portfolio can deliver significant savings in time and resources. Designs that can handle a wide range of battery voltages require high-efficiency operation with the capability to drive a wide range of MOSFET gate current and voltages, accommodate high thermal dissipation, and withstand very large negative transients.

This article discusses these challenges when trying to accommodate wide-ranging battery voltages and motor powers in a single driver design and presents a commercially available solution as a design case study.

To drive motors or drivers for high-voltage, high-power applications where low noise with high efficiency is the critical design factor, the continuing design trend is to use permanent magnetic synchronous motor (PMSM) drives and/or brushless DC (BLDC) drives. For many other applications, such as those where the acoustic noise of the mechanical processing usually drowns out the motor noise, simple DC motors that can be driven with a simple half-bridge architecture are still adequate.

Nevertheless, running a motor/driver with a wide power range causes power dissipation and switching effects that pose significant challenges for both three-phase drives and DC drives, so the considerations here are valid for both.

High-voltage and high-power DC motor operation

Running a DC motor may seem like a simple task. However, it still presents challenges, including the need to sustain high-voltage operation to support dissipation of motor inductance energy when braking. To address this challenge in applications where the driver stage must be suitable for use with a wide power range, designers require solutions that enable both high-voltage operation and the capability to handle huge negative transients.

A wide-ranging power solution also requires the capability to drive a wide range of gate currents for medium-power to high-power MOSFETs, which introduces high power dissipation inside the device. To address this power dissipation challenge, designers may find the best solutions in drivers with low driving impedances.

For a start, driving a MOSFET requires an understanding of the MOSFET switch waveform, discussed next.

Understanding MOSFET switching behavior

For inductive loads like motors, the switching cycle can be divided into four phases:

1. t₀ to t₁ → Gate voltage rises to the threshold voltage.
2. t₁ to t₂ → Drain current (i_D) rises, and gate voltage rises according to the transconductance of the MOSFET.
3. Drain-to-source voltage (V_DS) falls—not linearly because input capacitance (C_ISS), output capacitance (C_OSS), and reverse transfer capacitance (C_RSS) are dependent on V_DS—and the gate current charges the Miller capacitance (V_GS), during which time, V_GS is stable.
4. t₃ to t₄ → V_DS is saturated low, and V_GS rises to its final value.

These phases are illustrated in Figure 1.

Figure 1 Plot of voltages and currents over time for a MOSFET encompasses drain-to-source voltage (V_DS), gate-to-source voltage (V_GS), drain current (i_D), gate current (i_G), and threshold gate-to-source voltage (V_GS(th)). Source: Allegro Microsystems

The gate-to-source voltage at the start of Phase 1 (V_GS(t)) is zero, and the flow of the gate-drive current (i_G(t)) that the driver needs to supply is at its peak. This maximum drive strength is not needed for the total switching time (t₀ to t₄) because the gate capacity becomes successively charged.

Approximately, the typical turn-on time can be obtained by:

t_r(HS) = C_LOAD × R_DS(on)UP

Where:

• t_r(HS) is the time from t₀ to t₄,
• C_LOAD represents the gate capacitance of the MOSFET, and
• R_DS(on)UP is the pull-up on resistance.

In general, to keep the power budget low, fast switching is desired. On the other hand, in most cases, gate drive current needs to be limited to control switching speed—dV/dt—to meet electromagnetic compatibility (EMC) requirements.

By adding a gate resistor (R_GATE), turn-on time can be extended according to:

t_r(HS) = C_LOAD × (R_DS(on)UP + R_Gate)

Several effects need to be weighed when increasing the gate resistor. Increasing the gate resistor will:

• Increase the switching losses, leading to increase in the light red area in Figure 1.
• Decrease the demand for driving power from the gate driver. This effect is generally desirable because it results in less power dissipation from the driver itself, so less heat is produced. The tradeoff is a longer time to charge the total gate capacitance of the MOSFET and an increase in the power dissipated on the gate resistor, meaning a higher voltage drop occurs for a longer time. In other words, the power losses shift from the driver to the gate resistor.
• Increase the dead time.

The best tradeoff needs to be found to account for all these effects.

Understanding MOSFET fast-switching and Miller effect

In addition to the MOSFET switching behaviors and tradeoffs discussed above, fast switching can cause another appearance of the known Miller effect, which must be considered in a design. The Miller effect can lead to an induced V_GS bounce caused by a gate inrush current, according to:

I_G = C_GD × dV_DS/dt

The name stems from the gate-to-drain capacity of a MOSFET, also termed as the Miller capacity.

To illustrate the Miller effect, all MOSFET capacities in a half bridge are shown in Figure 2. The input capacitance (C_ISS), output capacitance (C_OSS), and reverse transfer capacitance (C_RSS)—values that are typically indicated in the MOSFET datasheet—are related to the gate-to-drain capacitance (C_GS), gate-to-source capacitance (C_GS), and drain-to-source capacitance (C_DS) as follows:

C_ISS = C_GD + C_GS

C_OSS = C_DS + C_GD

C_RSS = C_GD

These relations can be rewritten as:

C_GD = C_RSS (C_GD = Miller capacitance)

C_GS = C_ISS – C_RSS

C_DS = C_OSS – C_RSS

Figure 2 Here is a view of a half-bridge topology with MOSFET capacities. Source: Allegro Microsystems

An example of ideal gate drive signals of both the high side and the low side with sufficient dead time and with motor voltage monitored at the S node is shown in Figure 3. In contrast to this ideal, the high-side and low-side gate voltages might be observed in practice as shown in Figure 4. The difference between the ideal and the actual is explained by the switching behavior.

Figure 3 The diagram shows low-side (LS) gate voltage, high-side (HS) gate voltage, and motor voltage over time. Source: Allegro Microsystems

Figure 4 Another view shows low-side (LS) gate voltage, high-side (HS) gate voltage, and motor voltage over time with oscillation. Source: Allegro Microsystems

When switching on the high-side gate, the fast dV/dt transient of the S node causes the low-side gate voltage Miller capacitance (C_GD) to recharge, pulling the V_GS of the low-side MOSFET above the low-side gate threshold voltage (V_GS(th)). This leads to cross-conduction resulting in oscillation at the S node and extensive power losses. Reducing the low-side MOSFET gate resistor in contrast to the high-side MOSFET gate resistor and using an adequate snubber on the S node can mitigate this effect. Significant improvements can be reached by adding an additional ceramic capacitor in parallel to the high-side gate capacitance, which would reduce dV/dt.

Leveraging MOSFET capacities to avoid Miller effect

Here is a design case study used to avoid the Miller effect while employing the APEK89500 demonstration board designed to evaluate the A89500 half-bridge MOSFET driver. The A89500 fast-switching half-bridge MOSFET driver is designed to enable both high-voltage operation—for instance, high side and low side amounting to 2.7 A source current (typical)—and 5.2 A sink current (typical). It scales up to a 100 V bridge supply and handles up to –18 V transients at the high-side gate output terminal and the high-side source (load) terminal, as illustrated in Figure 5.

Figure 5 The diagram highlights the negative transient voltage sustainability. Source: Allegro Microsystems

With a dual-flat no-leads (DFN) package, A89500 has a very low package thermal-resistance junction to ambient (R_ƟJA)—38°C/W for a two-layer 3.8 × 3.8-inch PCB. To assist designers in understanding the maximum drive strength, the driver needs to supply throughout all phases from t₀ to t₄ of the switching cycle. The approximation used in this article for the charging time of a capacitor connected directly to the driver is also used in the datasheet, as shown in Table 1.

Table 1 Excerpts from datasheet highlight charging time of a capacitor connected directly to the driver. Source: Allegro Microsystems

The APEK89500 demonstration board designed to evaluate the A89500 driver demonstrates the capability of the A89500 to avoid the Miller effect and deliver low-noise, high-efficiency operation. The board deploys two MOSFETs with the capacitances, as shown in Table 2.

Table 2 Capacities shown are for the APEK89500GEJ-01-T or APEK89500KEJ-01-T demonstration board used with the A89500 fast-switching 100 V half-bridge MOSFET driver. Source: Allegro Microsystems

The APEK89500 demonstration board was set up without optimization for a reference design for the design target. This deliberate lack of optimization resulted in susceptibility to the Miller effect. Despite the lack of a reference design for the design target, the Miller effect could be completely canceled out by adding a 1-nF capacitor in parallel to the high-side gate capacitance C_GS. The reduction of the C_GD/C_GS ratio is shown in Table 3. When implementing designs that use the A89500, a good approach that completely avoids the Miller effect is to maintain a similar reduction ratio.

Table 3 Additional ground-to-source capacities are shown for the APEK89500GEJ-01-T or APEK89500KEJ-01-T) demonstration board used with the A89500 fast-switching 100 V half-bridge MOSFET driver. Source: Allegro Microsystems

As shown in this design use case, adding a capacitor in parallel to the high-side gate capacitance C_GS will cause a reduction in dV/dt at the S node and will therefore mitigate the Miller effect. This result can be leveraged by reducing the C_GD/C_GS ratio at the low side as well—for instance, by adding a capacitor parallel to the low-side gate capacitance. This approach becomes comprehensive when considering C_GD and C_GS as a voltage divider (Figure 6). Thus, when increasing C_GS, the apparent gate-to-source impedance becomes smaller, which further supports the effort to keep the gate well below V_GS(th).

Figure 6 Capacitive voltage divider at the gate takes into consideration the apparent impedance. Source: Allegro Microsystems

Of course, a proper C_GD/C_GS ratio can be obtained by using a MOSFET that is appropriate for the design. Additional measures to avoid a capacitive switch on the low side include using a low-side MOSFET gate resistor that is reduced in contrast to the high-side MOSFET gate resistor and a snubber on the S node to mitigate the effect of cross-conduction.

Christian Huber is senior field applications engineer at Allegro Microsystems.

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