Tariq Kurd, lead IP architect at Codasip, has won the RISC-V Technical Contributor Award from the RISC-V Board of Directors. He currently chairs the Code Size Reduction Task Group, tasked to develop a holistic solution for reducing code size and thus making RISC-V more competitive with existing embedded core architectures.
The group’s work is now close to ratification. It’s important to note that while this development work will lead to small, embedded cores that often have very constrained memory sizes, larger and higher-performance cores will also benefit from reduced code size.
Kurd is also the Chair of the Task Group for Zfinx, which focuses on sharing floating point and integer registers to save area and reduce context switch time. The work of the Zfinx Task Group has already been ratified. Additionally, he has contributed to the ratified ePMP specification for memory access and execution prevention on machine mode.
At Codasip, Kurd’s work mainly relates to the application core family and related aspects such as functional safety and security. He is also focusing on the specification for Codasip’s next-generation processor IPs, including L31, a small 32-bit RISC-V processor core aimed at embedded systems with more modest processing requirements.
Before joining Codasip, Kurd was at Huawei, where he led the company’s efforts to migrate processors to RISC-V architecture. “What will be my next contribution to the RISC-V Community, I do not know yet, but I have several ideas for making RISC-V even more competitive with other architectures,” he said on the news about receiving the award.