Comprising a silicon-proven PHY and controller, the Cadence LPDDR5X on-chip memory interface IP operates at data rates of up to 8533 Mbps. The new IP is 33% faster than the previous generation LPDDR IP and features a scalable and adaptable architecture to connect to LPDDR5X DRAM devices that comply with the JEDEC JESD209-5B standard. It is also based on the latest DFI 5.1 specification and supports a variety of on-chip buses.
LPDDR5X memory opens up a wide variety of high-bandwidth applications beyond the mobile market typically served by LPDDR memory, including advanced driver assistance systems (ADAS), autonomous driving, lower-end edge AI, and networking. Cadence LPDDR5X IP enables next-generation SoC designs for these and other applications with flexible floorplan design options. Further, the new architecture allows fine-tuning of power and performance based on individual application requirements.
At 8533 Mpbs, the design IP supports the fastest data rate defined by the JEDEC JESD209-5B standard. The LPDDR5X PHY and controller have been verified with Cadence’s Verification IP (VIP) for LPDDR5X to provide rapid IP and SoC verification closure. Cadence VIP for LPDDR5X includes a complete solution from IP to system-level verification with DFI VIP, LPDDR5X memory model, and system performance analyzer.
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