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SiC Wafer Trends to Know Prior to Implementation

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For design engineers working to implement silicon carbide (SiC) semiconductors into their solutions, understanding what’s currently in play on the SiC wafer and manufacturing front, how it affects them, and what’s coming next is critical.

SiC is a semiconductor compound in the wide-bandgap segment where semiconductors operate at higher voltages, frequencies and temperatures. Its wide bandgap and high thermal stability allow design engineers to use SiC devices at junction temperatures up to—and sometimes beyond—200 degrees Celcius. When Tesla chose to use SiC-based motor controllers in 2017, it opened the proverbial floodgates of high-volume SiC device development.

SiC enables higher switching frequency and operating temperature, greater efficiency, lower switching losses, high power density, improved thermal management, and reduced size and weight. Ultimately, the features result in smaller system devices and lower system cost.

Figure 1: A view of properties of Si, SiC and GaN and where each stands today. (Source: STMicroelectronics)

SiC fabrication: What to know

When implementing SiC into their solutions, what should design engineers understand about the manufacturing process and keep in mind regarding its use? Process optimization, SiC hardness and what it means, inherent challenges, and wafer reclaiming are all a part of that understanding.

SiC wafer process

High purity silicon and carbon powders are used to grow SiC single crystals. Multi-wire dicing is used to cut SiC crystals into slices with a thickness of 1 mm or less. The wafers are ground to a desired flatness via diamond slurry, then mechanically and chemically polished for mirror-surface SiC wafers. Next, optical microscopes are used to detect surface defects.

Then wafers are cleaned to remove surface contaminants and are dried. At this point, manufacturers can use several methods to generate SiC epitaxial wafers on substrates. Although final polishing is like silicon, the steps before final polishing are complex and processing times vary. Edge grind, for example, takes approximately five to 10 minutes per wafer; however, as grind wheel suppliers continue to address SiC, grind time is beginning to come down.

SiC hardness

Measuring 9.5 on the Mohs scale of hardness (just behind diamond), one would think SiC would also be durable. However, that assumption isn’t true. On the contrary, SiC is extremely fragile, which means it requires higher temperatures and more energy and time for crystals to grow.

It also takes much longer to slice a SiC puck, for example, than a silicon boule of the same diameter. Multiple wafers can be sliced simultaneously to yield 10 to 20 wafers in a single process run, but it can take up to 20 hours to get all the way through.

Wafer reclaiming

X-Trinsic, a provider for SiC services including wafering, reclaim, process solutions, and consulting, recently announced a wafer reclaiming scheme that enables wafers deemed unusable for devices to be reclaimed by removing a damaged surface layer. The wafer is then repolished to restore a device-ready surface, which is designed to lower cost.

Dopant/epitaxial layer

The thickness and dopant level of an epitaxial layer depends on the operating voltage and type of device to be made. Design engineers can either build devices on the SiC wafer, or grow an epitaxial layer for devices that require 600-, 900-, 1,200-V, and higher. The decision relates primarily to voltage. If epitaxy is required, thick layers take longer to grow.

SiC fabrication challenges

To date, one of the most difficult challenges is the transition from 100-mm wafers to 150-mm wafers. Increasing wafer size—and the next stop is 200-mm—typically creates challenges in eliminating surface defects and reliability of the semiconductor. Typical defects include crystalline stacking faults, micropipes, pits, scratches, stains, and surface particles that can affect device performance.

Fabrication times are slow compared with silicon, and SiC devices are less rugged. It’s no surprise then that SiC costs 3× more than that of silicon, yet overall system cost is lower due to smaller size of passive elements. Once mass produced, economies-of-scale cost reductions will follow.

Figure 2: SiC wafer technology is rapidly evolving in terms of size and features like defect detection. (Source: STMicroelectronics)

In the case of SiC, the transition from 150 mm to 200 mm may seem easier because, with minor upgrades, manufacturers already have lab equipment that can handle larger SiC wafers, according to Gianfranco DiMarco, manager for Wide Bandgap Technical Marketing at STMicroelectronics. “However, larger wafers require special care to address the higher defect density of the SiC substrates.”

He added that the cost of system ownership for SiC-based designs is competitive with silicon-based designs. A traction inverter with SiC enables designers to drastically cut losses due to heat dissipation, reduce the size of electronics, and shrink cooling systems, making them less expensive. The result is phenomenal as new car models have greater range for a given battery pack.

“The higher production volumes and the availability of 200-mm wafers will further boost cost competitiveness, making SiC even more attractive for a larger pool of users,” DiMarco said.

In other words, system-level efficiency gains of SiC devices over the lifetime of the products they’re designed into are more than sufficient to cover the energy investment necessary to grow and process the initial SiC material. In addition, the design will require fewer components yielding both space and weight savings.

SiC ecosystem expanding

SiC is expected to have an edge in the electric vehicle (EV) sector where manufacturers are rapidly moving to 800-V battery systems for efficient high-voltage operations. Moving to 800 V and keeping the current the same means double the power and fewer losses. Greater demand will naturally scale down manufacturing prices.

Then there are SiC tools made available to engineers to ensure first time right SiC products. Take Elite Power Simulator and Self-Service PLECS Model Generator (SSPMG), unveiled by onsemi at APEC 2023 in Orlando, Florida. “It’s well known that switching energy loss data is dependent on the parasitics of the measurements set ups and circuits,” said Noriko Fujiwara, marcom campaign manager at onsemi. “We’re enabling users to input the parasitics of their application to have models that are accurate.”

So, while you’re looking at manufacturing specifics, play close attention to advances in SiC wafer technology as well as how the SiC industry continues to make design easier, faster and more accurate.

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