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Test-generation library verifies RISC-V processors

Integrity FASTApps from Breker is a library of automated test-generation IP elements that provides high-coverage verification for RISC-V processor cores and SoCs. Specific test sets are provided for verifying the integrity of both processors and SoCs that use the freely available RISC-V Open Instruction Set Architecture (ISA).

“The RISC-V Open ISA concept, while powerful, introduces verification challenges to engineering teams unfamiliar with processor complexities,” observes David Kelf, Breker’s CEO, an active RISC-V Consortium member involved with a public effort to improve RISC-V verification methodologies. “By automating test content generation, Breker’s years of verification experience can be encapsulated and applied across many projects, driving high test coverage with a minimal level of effort.”

Processor Core Integrity FASTApps include common, but hard-to-verify scenarios such as load store integrity, random instruction testing, register-to-register hazards, conditionals and branches, exceptions, async interrupts, privilege level switching, core security, exception testing (memory protection and machine-code integrity), virtual memory/paging, and core coherency.

In addition, SoC Integrity FASTApps include random memory and register tests, system interrupt testing (external, timing, and software interrupts), multi-core execution, memory ordering, atomic operations, system coherency, system paging and memory management unit (MMU) operations, system security, and power management.

Integrity FASTApps for RISC-V, as well as Arm and X86 based systems, are available today. Pricing is available upon request, with special introductory pricing for FASTApps.

Integrity FASTApps product page

Breker Verification Systems

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